Mounted on the S3CP there are 4 DSPs working in a systolic cluster and an FPGA for hardwired processing and microprocessor activity. Conversion is made through IF Analog to the Digital path, where the analog signal is sampled by the AD converter at 150 MPs/s. The BF analog signal is sampled , using a 16 bit 2.5 MPs/s converter. The RS signal is generated from a DDS, with a 1 GHz NCO allowing the user to generate a wide range of different modulation schemes, using the I/Q datapath from the FPGA/DSPs.
A wide range of applications are possible. A FPGA microprocessor developed using Microblaze™ XILINX core, is available to manage all the parts on the board.
A fully compliant cPCI bus standard allows users to communicate with more than one board over a cPCI backplane (Microprocessor unit is needed).
A GPS receiver and a high stability OCXO guarantee that all the processing inside the FPGAs/DSPs are synchronous or time referenced via a built-in NTP server.
In the next hardware release the physical interface will be compliant with the PTP protocol (IEEE1588) and enable timestamping of real time events occurring in the host O.S. or triggered on the external SMB connectors.
Software